This invention relates to synchronization of an oscillator output to a pulse train and, more particularly, to a method and apparatus for synchronizing an oscillator to a bunched, i.e., pulse-swallowed, or rapidly jittering pulse train.
In communications systems, there are a number of applications in which it is necessary to generate a smooth, i.e., regularly occurring, pulse train from a bunched, i.e., pulse-swallowed, or rapidly jittering pulse train. For example, pulse-swallowed data might result after error correction of a data stream or removal of framing codes. Recovering a low-jitter clock from such pulse-swallowed data can be a challenge, particularly in applications that require the capability of generating a range of clock frequencies. If CMOS technology is used in a communications system, clock recovery is additionally hampered by the high self-noise inherent in CMOS oscillators.